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Digital Pulse Density Signal Technology

Fabricated in a 2-micron CMOS process, the digital ASIC functions as a sigma-delta type capacitance-to-frequency converter. The ASIC modulates the capacitive sense element and monitors the effect of accelerations on the sense element via the sense amplifier. The comparator then demodulates the output of the sense amplifier to form the (sigma-delta type) pulse density digital output.

The digital section of the ASIC is driven by an external clock source and controls the sequence in which the reference voltages are switched onto the sense elements' capacitor plates. Non-volatile PROM and D/A converters are used to generate these reference voltages and provide a method of calibrating the accelerometer, thus compensating for the bias and scale factor fabrication tolerances of the sense element.
 

The digital output from the electronics allows direct connection to an inexpensive microprocessor or digital counter without requiring a separate analog-to-digital converter. This type of output also provides substantial insensitivity to electromagnetic interference (EMI) compared with low level analog signals.

 

 

The pulse density output signal consists of a series of logic pulses and the pulse rate of this signal is linearly proportional to the applied acceleration. The output pulse rate varies from no pulses per second for negative full scale acceleration to the maximum pulse rate (equal to the input clock frequency) for positive full scale acceleration. At zero acceleration, the pulse rate is nominally equal to one-half the input clock rate